This invention relates to circuits for testing transistors or FET devices for satisfactory gain both in-circuit and out-of-circuit.
Until the recent development of improved testing apparatus, transistor devices could not be tested reliably and safely without disconnecting them from the circuits in which they are used. When testing transistors in-circuit, with most prior art testing apparatus there was a significant risk of damaging the circuits involved, particularly where the transistors were shunted with low impedences. Thus, if DC voltages or continuous square wave voltages are applied to a heavily shunted transistor, the resulting energy supplied to those circuits could be excessive and destroy associated circuit components.
In recent years there was developed a transistor testing circuit using pulsed test voltage waveforms with a low duty cycle which permits transistors to be tested safely in-circuit. Such a testing circuit is disclosed and claimed in U.S. Pat. No. 3,870,953 to Boatman, et al. In this circuit, square-topped pulse waveforms are provided for both the emitter-collector (load) terminals and the base (control) terminals of the transistor devices to be tested which automatically periodically establish the voltage conditions during successive testing intervals which test respectively NPN and PNP type transistors. These emitter-collector and base drive voltages are intermittently applied so that insufficient energy is applied to the transistors tested in-circuit to damage the transistors or the associated circuit components, even when low shunting impedances are present.
This transistor testing apparatus, however, did not provide for the testing of FET devices, and in other respects did not give the operator maximum aid in carrying out leakage and material type tests, or enable the operator to select different control terminal drive levels, as in the case of the present invention to be described, which has unexpected advantages to be described.
The present invention, therefore, represents an improvement over the testing apparatus which is the subject of said U.S. Pat. No. 3,870,953.
Accordingly, one of the objects of the invention is to provide improved transistor testing apparatus operating on the principle of that disclosed in said U.S. Pat. No. 3,870,953, and which further permits the use of such apparatus in the testing of FET devices.
Another object of the invention is to provide transistor and FET testing apparatus as described which gives the operator greater flexibility in his testing of the devices involved. A related object of the invention is to provide transistor and FET testing apparatus which makes it simpler for the operator to carry out material type and leakage tests where the initial testing of the devices raises the question as to whether or not the devices have excessive leakage.